Now multi-bit soft errors are becoming increasingly on-chip L2 caches due to increase in the chip density due to technology scaling and decrease in the minimum feature size. Due to increase in multi-bit errors we will face biggest problems like corruption of data and crashing of application programs. Normally, the techniques like Error detection/correction codes, Physical interleaving of cache bit lines to convert multi-bit errors into single-bit errors; and Cache scrubbing will protect the L2 caches from the soft errors. In this report, we will investigate about multi-bit soft error rates in large L2 caches and to solve these errors we develop a framework of solutions using amount of redundancy present in the memory hierarchy. We will check various new techniques to reduce the no. of multi-bit errors in large L2 caches, in which, simple error detection codes will detect the multi-bit errors and by using data redundancy in the memory hierarchy we will solve the multi-bit errors.

We also propose several techniques to control/mine the redundancy in the memory hierarchy to further improve the reliability of the L2 cache. The proposed techniques were implemented in the Simple scalar framework and validated using the SPEC 2000 integer and floating point benchmarks for L2 cache vulnerability, global cache miss-rate, average cycle count and main memory write back rate, considering the area and power overheads. Experimental results indicate that the vulnerability of L2 caches can be decreased by 40% on the average for integer benchmarks and 32% on the average for floating point benchmarks, with average multi-bit error coverage of about 96%, with significantly less area and power overheads and with virtually no performance penalty. The proposed techniques can be applied to both single and multi-core processor-based systems. They are developed to decrease the multi-bit errors in the L2 caches.

PROPOSED SYSTEM:

In the proposed system, simple error detection codes will detect the multi-bit errors and data redundancy in the memory hierarchy will solve this errors. This system consumes less architecture area and also power consumption of new system is less when compared with existing system.

LANGUAGE USED: VHSIC Hardware Description Language (VHDL)

TOOLS REQUIRED:

Simulation: modelsim5.8c

Synthesis: Xilinx 9.1