Bhuvish
Now multi-bit soft errors are becoming increasingly on-chip L2 caches due to increase in the chip density due to technology scaling and decrease in the minimum feature size. Due to increase in multi-bit errors we will face biggest problems like corruption of data and crashing of application programs. Normally, the techniques like Error detection/correction codes, Physical interleaving of cache bit lines to convert multi-bit errors into single-bit errors; and Cache scrubbing will protect the L2 caches from the soft errors. In this report, we will investigate about multi-bit soft error rates in large L2 caches and to solve these errors we develop a framework of solutions using amount of redundancy present in the memory hierarchy. We will check various new techniques to reduce the no. of multi-bit errors in large L2 caches, in which, simple error detection codes will detect the multi-bit errors and by using data redundancy in the memory hierarchy we will solve the multi-bit errors.
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