VLSI Projects Archives – Page 2 of 3 – Student Project Guidance & Development

Building AMBA AHB Compliant Memory Controller

Bhuvish October 1, 2013

Building An AMBA AHB Compliant Memory Controller

Nowadays performance of the microprocessor is improved rapidly. In contrast, bandwidths and memory latencies are less improved. The final result is, the system performance is limited by the memory access time. To solve this problem we designed and developed the Memory Controller (MC). The memory controller will control the memory of the system and it is integrated into the system chipset. It is a main part of the system. In this paper we explained how to develop an Advanced Micro controller Bus Architecture (AMBA) compliant MC as an Advanced High-performance Bus (AHB) slave.

AMBA- Advanced High Performance Bus IP Block

Bhuvish August 23, 2013

The Advanced High-performance Bus (AHB) is a member of AMBA (Advanced Micro controller Bus Architecture) family. This high performance bus is useful in the high clock frequency system modules. AHB supports connection between low-power peripheral macro cell functions and on-chip memories & off-chip external memory, the efficient connection of processors. The AHB performs as the high-performance system backbone bus. With the help of synthesis and automated test techniques, AHB is specified to ensure ease of use in an efficient design flow.

ASIC Design of Complex Multiplier

Bhuvish August 12, 2013

ASIC Design Of Complex Multiplier An old methodology of Indian mathematics which has a unique technique of calculations based on 16 Formulae is called as Vedic mathematics. In this paper, we are proposing a high-speed complex multiplier design (ASIC) by using Vedic Mathematics. We designed the multiplier and adder/sub-tractor unit with the help of ancient Indian mathematics i.e. Vedas. We can generate the partial products and sums in one step & can reduce the carry propagation from LSB to MSB by using those formulas. Read more about ASIC Design of Complex Multiplier …

Asynchronous Transfer Mode Knockout Switch

Bhuvish August 6, 2013

Asynchronous Transfer Mode Knockout Switch

Asynchronous Transfer Mode Knockout Switch – An N-input N-output packet switch in which all inputs and outputs are working at the same bit rate is called as the Knockout Switch. Each fixed-length packet contains the address of the output port and in a time-slotted style, fixed-length packets arrives on the N-input. The Knockout switch has application in both virtual circuit and Datagram packet networks. We can control the average number of packet arrivals destined for a given output but we have no control on the specific arrival time of packets, on the inputs and their associated output addresses.

Adiabatic Technique for Energy Efficient Logic Circuits Design

Bhuvish July 15, 2013

Adiabatic technique is used to minimize the energy dissipation in conventional CMOS circuits. Also this technique will recycle the energy stored at load capacitance instead of losing that energy as heat and minimizes the dissipation in PMOS network.

But variation in parameter will play an important role in this adiabatic technique. This parameter variation will analyze the energy consumption by using TSPICE simulations.

A Processor-In-Memory Architecture for Multimedia Compression

Bhuvish July 2, 2013

A Processor-In-Memory Architecture for Multimedia Compression

In this proposed project, we are developing a low complexity processor in memory (PIM) architecture for compressing the size of image and video. We can reduce the latency of SRAM and improve its bandwidth by integrating a Novel processing element with Static random-access memory (SRAM). To decrease the power, area, cost and complexity we proposed various PIM design techniques in this paper. A design methodology is provided by an analysis of the processing element capabilities and performance. The proposed architecture consumes very less area and gives higher output.