Building AMBA AHB Compliant Memory Controller

Building An AMBA AHB Compliant Memory Controller

Nowadays performance of the microprocessor is improved rapidly. In contrast, bandwidths and memory latencies are less improved. The final result is, the system performance is limited by the memory access time. To solve this problem we designed and developed the Memory Controller (MC). The memory controller will control the memory of the system and it is integrated into the system chipset. It is a main part of the system. In this paper we explained how to develop an Advanced Micro controller Bus Architecture (AMBA) compliant MC as an Advanced High-performance Bus (AHB) slave.

Main memory consists of SRAM and RAM. We developed MC to control the system memory. In this paper, we explained the problems faced in the design process and we also explained the solutions given to those problems.

Building An AMBA AHB Compliant Memory Controller


We developed this project using VHSIC Hardware Description Language (VHDL).

VHSIC – Very High Speed Integrated Circuit


ModelSim XE III 6.4b: is used for Simulation.

Xilinx ISE 10.1: is used for Synthesis.

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