ASIC Design of Complex Multiplier

An old methodology of Indian mathematics which has a unique technique of calculations based on 16 Formulae is called as Vedic mathematics. In this paper, we are proposing a high-speed complex multiplier design (ASIC) by using Vedic Mathematics. We designed the multiplier and adder/sub-tractor unit with the help of ancient Indian mathematics i.e. Vedas. We can generate the partial products and sums in one step & can reduce the carry propagation from LSB to MSB by using those formulas.

We can reduce the propagation delay by implementing the Vedic mathematics and their application to the complex multiplier. This implementation is better than parallel adder based implementation and DA based architecture.

Spice spectre checks the functionality of these circuits and calculates the performance parameters like propagation delay and dynamic power consumption with the help of standard 90nm CMOS technology.

The resulting (16, 16)×(16, 16) complex multiplier consumes only 6.5 mega watt power and its propagation delay is just 4ns. By using the complex multipliers like parallel adder and DA based architectures, we achieved only 25% improvement in the speed.

Project title: ASIC Design of Complex Multiplier

LANGUAGE USED:

This project is developed by using VHSIC Hardware Description Language (VHDL).

VHSIC – Very High Speed Integrated Circuit

TOOLS REQUIRED:

ModelSim XE III XE III 6.4b: is used for Simulation.

Xilinx ISE 10.1: is used for Synthesis.

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